Performance and test methods of the thirdorder digitalltiplex equipment operating at 3468 kbit sand using poive justification 34368 kbit s正码速调整三次群数字复用设备技术要求和测试方法
3.
Performance and test methods of the second order digital multiplex equipment operating at 8448 kbit s and using positive justification 8448 kbit s正码速调整二次群数字复用设备技术要求和测试方法
4.
Performance and test methods of the fourth order digital multiplex equimpent operating at 139264 kbit s and using positive justification 139264 kbit s正码速调整四次群数字复用设备技术要求和测试方法
5.
The clock obtaining practical circuit in approximately synchronization and clock circuit about symbol synchronization are designed ( realized one circuit ) ; the three controlling circuits with fast and low clock in code speed adjust technique are designed 在此基础上设计了基于scc准同步的一种时钟恢复实现电路和两种字符型起止式同步电路(实现了一种) 。设计了正码速调整技术中快慢时钟的三种控制电路。
