Chinese translation for "并串"
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- paralleled-to-serial
Related Translations:
- Example Sentences:
| 1. | Parallel - serial converter serializer
并串变换器 | | 2. | Parallel serial conversion p s
并串变换 | | 3. | According to this method , a new matching criterion of coupling slots is derived for the series - series feeder and the shunt - series feeder
按照同样方法，对串串、并串形式的馈电装置，导出了新的耦合裂缝匹配设计准则。 | | 4. | In the modulation / demodulation circuits , cpld is selected as platform of the digital logic part , which includes series - shunt / shunt - series transform , difference coding and sample verdict
调制/解调电路中，串并/并串变换、差分编/解码和抽样判决等数字逻辑部分是以cpld作为开发平台，论文给出了实现上述功能的vhdl程序及仿真、测试结果。 | | 5. | The receiver unit mainly consisted of the digital down converter , matched filter , integration and dump module , power detector , symbol tracking processor , differential demodulator , parallel - to - serial conversion module , output processor and afc module
接收部分主要有数字下变频、数字匹配滤波器、积分清洗、功率检测、符号跟踪处理、差分解调、并串处理、自动频率跟踪处理等模块。 | | 6. | This hardware system absorbed simd and mimd parallel structure ' s merit in the maximum extent , it can be used not only to realize parallel type neural network algorithm , but also to realize parallel and serial type neural network algorithm and other parallel algorithm
该硬件系统最大限度地吸收了simd和mimd两种并行结构的优点，既可以用于实现并型神经网络算法，又可以用于实现并串型神经网络算法及其他并行算法。 | | 7. | To reduce voltage stress of transformer secondly diodes , a novel parallel - parallel / serial type cttfc is presnt . it has many attractive characteristics , such as low current stress of power switches , small intput and output filter size , high reliability , and sharing output voltage
提出了一种并?并串型双管正激组合变换器，该组合变换器具有副边二极管电压应力低、开关管电流应力小、输出均压、输入输出滤波器体积小等优点。 | | 8. | Furthermore , we use the matlab simulation result to analyze the capability of viterbi decoding . finally , we complete the fpga designing of each module in the base - band processing unit , including parallel - to - serial conversion module , framing module , convolutional coding module in the sending end , serial to parallel conversion module , viterbi
基带处理单元各模块的fpga设计主要包括发送端并串转换模块、成帧模块、卷积编码模块、接收端串并转换模块和viterbi译码模块,应用quartusii5 . 1开发平台以及modelsim仿真软件,给出了仿真结果。 |
- Similar Words：
- "并川" Chinese translation, "并川里" Chinese translation, "并穿越那阴霾 把信念握在手中" Chinese translation, "并传导神经冲动" Chinese translation, "并船舷" Chinese translation, "并串变换器" Chinese translation, "并串联" Chinese translation, "并串联变换器" Chinese translation, "并串联电路" Chinese translation, "并串联电容器组" Chinese translation
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