Chinese translation for "串并转换"
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- deserialize
Related Translations:
串: Ⅰ动词1.(连贯) string together 短语和例子贯串 run through; permeate; 把珠子串起来 string the beads together2.(勾结) conspire; gang up 短语和例子串骗 gang up and swindle sb.3.(错误地连接) get things mixed up 短语和例子电话串线 get 记忆串串: colorful memortmemories 串 串操作: serial serial operation 串接线: tandem transit routing 串接: base downbase upcascade connectionconcatenationconnect in seriesjoining up inseriestandem connection
- Example Sentences:
| 1. | An implement of english - mongolian machine translation system
语言设计实现单片机串行口输出的串并转换 | | 2. | Element don t have to be deserialized and reserialized to move from one document to the next
元素的内容从一个文档移到另一个文档并不需要串并转换或重新序列化。 | | 3. | The chip ' s function includes transmitter - receiver of lvds signal and serializer - deserializer of cmos digital signal
该芯片的功能包括lvds信号的收发以及cmos数据的串并转换。 | | 4. | An optical filter on infrared band and an optical tube for gathering light are also used . finally , the design of controller with complex programmed logic device chips and mcu are presented in this thesis , both of the hardware and software included . the system works well at 4mbit / s
最后,控制系统的设计采用了单片机和cpld的组合结构,以单片机为控制核心,由cpld实现编码解码及串并转换等数据处理,并完成了所有硬件的设计和软件编程及仿真测试。 | | 5. | The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach . the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures , and makes a lot of verilog simulation and verification on the circuits designed
串并模块串行化器和解串行器采用标准单元的方法设计，论文讨论了对几种时钟同步模式以及串并转换电路结构的权衡和实现，并对所设计的电路结构进行了verilog模拟验证。 | | 6. | Furthermore , we use the matlab simulation result to analyze the capability of viterbi decoding . finally , we complete the fpga designing of each module in the base - band processing unit , including parallel - to - serial conversion module , framing module , convolutional coding module in the sending end , serial to parallel conversion module , viterbi
基带处理单元各模块的fpga设计主要包括发送端并串转换模块、成帧模块、卷积编码模块、接收端串并转换模块和viterbi译码模块,应用quartusii5 . 1开发平台以及modelsim仿真软件,给出了仿真结果。 | | 7. | In addition , make out in detail the design on inner combination logic and time logic of fpga , including series - parallel conversion , data selector , counter , flip - latch , timer , encoder , etc . at one time , not only pursuit flow of the data gathering system is illuminated , but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework
另外，详细的介绍了fpga内部的组合逻辑和时序逻辑的设计方案，包括串并转换、数据选择器、计数器、锁存器、定时器、译码器等。并阐述了数据采集系统的工作流程，而且合理有效地使用了fpga内部的ram资源，将其构建成乒乓式结构。 | | 8. | Thirdly , the hardware platform of the video analysis system was detailed , and the system ’ s whole structure 、 video decoder 、 network control module and uarat control module were gone deep into one by one . finally , the software design of video analysis was deeply discussed . and the emphases were put on four aspects : one was the conversion from serial to parallel and other was the conversion between luminance and chroma , another was the method of video analysis , and the last one was the network compression technique of video stream
本文首先介绍了课题背景、研究现状及研究内容;然后叙述了ti的dsp功能、特性及应用技术;接着详细阐述了基于dm642的视频分析系统硬件设计,深入研究了视频分析系统的体系结构、视频解码模块、网络控制模块和串口控制模块;最后充分讨论了基于dm642的视频分析系统软件设计,重点探讨了视频数据的串并转换方法、色度空间转换方法、视频分析方法和网络视频压缩方法等。 |
- Similar Words：
- "串并行数据转换器" Chinese translation, "串并行系统" Chinese translation, "串并行转换" Chinese translation, "串并行转换器" Chinese translation, "串并行转换器串并转换器" Chinese translation, "串并转换 解串 并行化" Chinese translation, "串并转换器" Chinese translation, "串部件" Chinese translation, "串参数" Chinese translation, "串操作" Chinese translation
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