| 1. | Fill in the “ internet product login application form ” with legal person sign and stamp
填写附件中的进网表,要求法人签字盖章(两页) |
| 2. | Furthermore , timing simulation and static - state timing analysis were made . by doing these , netlist files were got
并进一步做时序仿真和静态时序分析,产生输出网表文件,最后下载到fpga进行系统实现。 |
| 3. | In the paper , we will focus on the digital module backend design , which is one of important application fields of ic
本文详细介绍了,数字机顶盒芯片的数字模块后端设计工作,从得到门级网表到交出gdsii研究开发的全过程。 |
| 4. | According to the hardware structure of the main experiment board , the circuit netlist transformation program translates the visual circuit description to the actual netlist
根据实验主板的硬件结构，设计的专用电路网表转化程序，将便于用户理解的图形化的电路描述转化为便于实际硬件操作的电路网表。 |
| 5. | It induces logic and delay to waveform , and describes the continuous states of nodes in netlist by waveform . it can realize simulating continuous states for integrated circuits by computing waveforms
它把逻辑和延迟有机地结合起来归纳为波形，并用波形来描述电路网表中节点的连续时间状态，通过对波形的计算实现整个电路的连续时间状态模拟。 |
| 6. | But circuitry net table which is synthesized by synthesizer is not necessarily achieve the demand of designer , so aim for the speed demand of destination , the sequence circuit which is synthesized demand speed optimization
但是由于综合器综合得到的电路网表不一定能达到设计者的设计要求，所以需针对给定的速度要求，对综合得到的时序电路进行速度优化。 |
| 7. | Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist , so for obtaining correct simulation result , i must have logic computing correctly and delay analysis accuracily
由于数字电路的模拟是基于对电路网表中的元件进行逻辑和延时计算的，所以要想得到正确的模拟结果，必须进行正确的逻辑运算和准确的延时分析。 |
| 8. | The project of developing the core comes from a national key program in science and technologies , study on mcu high level language description and embeded system technology . the project is followed the top - down design way
这个项目遵循了自上而下的设计流程，从系统划分、编写代码、 rtl仿真、综合、门级仿真，到布局布线、电气规则检查、设计规则检查，网表比较等。 |
| 9. | Recurring to the circuit netlist , the mcu of the main board finishes the digital setting for the parameters and the structure of the experiment circuit , which realize to do all kinds of electronics experiments in the same main experiment board
控制实验主板的单片机借助于电路网表所提供的信息，完成实验电路结构和参数的全数字化设置，从而实现了在同一实验主板上完成不同的电工电子实验。 |
| 10. | Then describes the 4 function modules in vhdl , the vhdl programs have passed compile and debug in maxplus ii , the results of function simulation and timing simulation all prove that the design is correct , at last , maxplus ii generates a netlist file which can be download into chip
然后使用vhdl硬件描述语言对四大功能模块进行描述，在maxplus环境下编译、调试通过，功能仿真和时序仿真结果证明设计正确，最后生成可下载的网表文件。 |
