| 1. | Design basis of combinational logic circuit
组合逻辑电路设计基础 |
| 2. | Digital combined logic circuit modeling and simulation based on matlab
的数字组合逻辑电路建模与仿真 |
| 3. | Analysis of competition and adventure in assembled - logic circuits using pspice simulation
分析组合逻辑电路中的竞争冒险 |
| 4. | Combinational logic circuit
组合逻辑电路 |
| 5. | The analysis and designation on the assembly logic circuit is one of the important content of digital circuit
组合逻辑电路的分析设计是数字电路重点内容之一。 |
| 6. | The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。 |
| 7. | It can give bdd presentation of boolean function or arbitrary combination logic circuits which are presented by cdl , and can realize different operation of boolean function by the operation to bdd
能完成对任意基于cdl语言描述的组合逻辑电路或布尔函数，实现其bdd表示并通过对bdd的操作实现对相应组合电路或布尔函数的操作。 |
| 8. | Digital design ： binary system , boolean algebra , logic gates , simplification of boolean functions , combinational logic . analog design ： amplifiers , frequency response , feedback , operational amplifier
数位设计：二进位制、布氏代数、逻辑闸、布氏函数的化简、组合逻辑电路。类比设计：放大器、频率响应、反馈系统、运算放大器。 |
| 9. | Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co . and the detailed analyses of typical examples are also given
结合altera公司classicep610芯片的结构，研究了将演化算法应用于函数级数字组合逻辑电路的硬件演化，并且对典型实例进行了详细分析。 |
| 10. | Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit , the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment , it has no function of memory
摘要数字电路分为组合逻辑电路和时序逻辑电路两类，组合逻辑电路的特点是输出信号只是该时的输入信号的函数，与别时刻的输入状态无关，它是无记忆功能的。 |
