English translation for "浮点加"

floating add

Related Translations:

浮点:  [计算机] floating decimal; floating point

浮点累加器:  electric accumulatorfloating accumulatorfloating point accumulatorfloating-point accumulator

浮点型:  float point typefloat typefloating typefloating-point types

浮点格式:  floating-point format

浮点减:  floating subtract

浮点二进制:  floating-point binary

浮点精密度:  precision floating-pointprecision, floating-point

浮点软件包:  floating-point package

浮点方式:  floating-point mode

浮点协处理器:  floating-point coprocessor

Example Sentences:

	1.	1 schmookler m s , nowka k j . leading zero anticipation and detection - a comparison of methods . in proc . 15th ieee symposium on computer arithmetic , vail , co , usa , june 11 - 13 , 2001 , pp . 7 - 12 该前导0预测纠正算法对于尾数和为正数或者负数的情况下都能正确工作，因此不需要事先判断尾数大小和进行尾数交换，适合在基于双通路结构的高性能浮点加减运算中采用。
	2.	And so on . as you can see , for a six - step floating - point addition , the speedup factor will be very close to six times at start and end , not all six stages are active as all stages are active at any given instant shown in red in figure 2 正如您可以看到的一样，对于一个6级的浮点加运算来说，加速比非常接近于6 （在开始和结束时，这六个步骤并不是都处于活动状态的） ，因为在任何给定的时刻（图2所示的红色） ，这些步骤都是活动的。
	3.	2 montoye r k , hokenek e , runyon s l . design of the ibm risc system 6000 floating - point execution unit . ibm journal of research and development , 1990 , 34 : 59 - 71 . 3 oberman s . floating - point arithmetic unit including an efficient close data path 我们采用90纳米cmos标准单元工艺以及synopsys自动布局布线流程进行实验，实验结果表明该算法在高性能双通路结构的浮点加减运算中引入后，可以使得近路径的运算延迟整体降低10 . 2 % ，且算法本身没有造成新的关键路径。
	4.	26th ieee asilomar conference on signals , systems , and computers , pacific grove , ca , usa , october 26 - 28 , 1992 , pp . 391 - 395 . 14 oklobdzija v . an algorithmic and novel design of a leading zero detector circuit : comparison with logic synthesis . ieee transactions on vlsi systems , 1993 , 2 : 124 - 128 而另一方面，该算法与目前国际上其它类似算法相比具有面积和功耗上的明显优势，根据实验结果，采用该算法所实现的电路面积比采用以往类似算法所实现的电路面积减少了27 ，功耗则降低了28 ，因此特别适合在高性能低功耗的浮点加减运算算法中采用。
	5.	The algorithm and its implementation of the leading zero anticipation are very vital for the performance of a high - speed floating - point adder in today s state of art microprocessor design . unfortunately , in predicting " shift amount " by a conventional lza design , the result could be off by one position . this paper presents a novel parallel error detection algorithm for a general - case lza 目前国际上已有很多算法对前导0预测算法进行了研究，但是出于设计方法和延迟等方面的限制，大部分前导0预测算法都为非精确算法，其预测结果可能与真实加法结果中前导0的个数产生一位的误差，这个误差需要在浮点加法的后规格化过程中进行修正，因此反过来又增加了浮点加减算法的关键路径延迟。
	6.	The proposed approach enables parallel execution of conventional lza and its error detection , so that the error - indication signal can be generated earlier in the stage of normalization , thus reducing the critical path and improving overall performance . the circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work 本文提出了一种新型的基于错误纠正机制的前导0预测算法，该算法在传统非精确算法的基础上增加了对其结果出错时的预判机制和规格化过程中的实时纠正机制，从而实现了尾数和规格化时的精确移位，降低了浮点加减运算的关键路径延迟。

Similar Words：

"浮点计算机" English translation, "浮点计位数" English translation, "浮点记号" English translation, "浮点记录系统" English translation, "浮点记数法" English translation, "浮点加法器" English translation, "浮点加速器" English translation, "浮点减" English translation, "浮点减法器" English translation, "浮点阶" English translation