English translation for "形式验证"

formal verification

Related Translations:

验证测量:  confirmatory measurementconfirmatorymeasurement

表层形式:  surface form

正规形式:  hessenberg-form hessenberg form hessenberg

交际形式:  forms of communication

扩展形式:  extend typestretched form

形式矢量:  symbolic vector

意大利形式:  italianare

形式电荷:  formal charge

典范形式:  canonical formcanonical transformation

形式标号:  form label

Example Sentences:

	1.	And formal verification is one form of static verification 其中形式验证是静态验证的一种。
	2.	Formal verification of hybrid systems 混合系统的形式验证方法
	3.	Formal verification of hybrid systems and its application on chemical process control 逻辑控制器的形式验证及其应用
	4.	This paper analyses patial sequential theory of formal verification , states the principle of modeling complex systems 本文通过对形式验证中部分顺序理论的分析，阐述了通过串并行部序集描述复杂系统的原理。
	5.	The glossary significance finally manifests in the syntax structure by a certain form , the verb valence may carry on the formal verification in the syntax structure 词汇意义最终在句法结构中以一定形式体现出来，动词的价可以在句法结构中进行形式验证。
	6.	After evaluating synopsys ' s formality , the paper construes the flow and practical experiences in video post - process chip , and comes to the conclusion that static verification really works 在简单评价了synopsys公司的商用软件formality之后，重点分析了在视频后处理芯片项目中formality的应用流程和实际工作经验，证明形式验证的重要作用。
	7.	This paper is composed of four parts . the first part discusses about the strategy of verification ; the second one analyzes vera ; the third focuses on the anatomy of verification work in video post - process chip version 2 , the last one probes into the formal verification theory , and summarizes the flow according to practical experiences 这篇论文分成四个部分，第一部分主要是对验证策略的介绍，第二部分是介绍vera语言的特性，第三部分是视频后处理第二版芯片中的验证工作的分析和总结，第四部分是对形式验证理论的探讨和视频后处理芯片中形式验证工具的使用以及经验的总结。
	8.	It presents the verification strategy used in the whole eda design flow of the chip . the simulation on module level ( inc . post - layout ) uses the software event - driven simulator , the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator , for the gate - level netlist produced by using top - down design flow , the sta tool can analyze the static timing , and more formal verification is used to ensure the correct function 本章还提出了系统在整个eda设计流程中的设计验证策略方法：模块级的模拟(包括布线后的模拟)全部采用事件驱动式的软件模拟工具来验证，各大模块的联合模拟及整个芯片的功能验证(寄存器传输级与门级)使用基于周期的模拟工具和硬件仿真器；对于采用top - down的设计方法得到的门级网表使用专门的静态时序分析工具来进行时序分析以及采用形式验证来保证正确的功能。

Similar Words：

"形式性测试" English translation, "形式性评量" English translation, "形式训练" English translation, "形式训练说" English translation, "形式衍生字符串" English translation, "形式要求" English translation, "形式液" English translation, "形式遗传学" English translation, "形式意义" English translation, "形式因" English translation