| 1. | Vhsic hardware description language and realization of data encryption
与数据加密的实现 |
| 2. | Vhsic - very high speed integrated circuit
超高速集成电路 |
| 3. | An 8 bits scm was designed with vhsic hardware description language ( vhdl )
课题采用硬件描述语言vhdl设计了8位单片机系统。 |
| 4. | To meet these requirements the system was designed as a custom digital logic component described in the standard hardware description language vhdl ( vhsic hardware description language )
为了实现这些要求，本设计采用vhdl ( vhsichardwaredescriptionlanguage )硬件描述语言设计实现。 |
| 5. | This paper has used the hardware language vhdl ( vhsic hardware description language ) to program some special circuit and prepared some work for the system on chip ( soc )
利用硬件描述语言将调速控制所需的一些电路综合在fpga芯片上为电机控制器向片内系统( soc )方向发展做了一定的工作。 |
| 6. | Introduce the characters of fpga and vhsic hardware description language , design the fast walsh - hadamard transfer on the epf10k30 chip , analyze the problems brought by the improper parts of the program design and give the solution
介绍fpga和vhdl语言的特点，设计快速沃尔什?哈达马变换在可编程器件epf10k30芯片上的实现过程，并对软件设计中的产生问题进行了分析，研究出解决的办法。 |
| 7. | In view of numerous digital and analog signals need to be processed , and the difficulty of real - time processing of multi channel 400 hz ac signal , vhdl ( vhsic hardware description language ) is applied to design the digital circuit , which is successfully realized in field programmable gates array ic - xc2s100
针对i o模块中需要处理的数字量和模拟量较多的事实，以及多路400hz信号的实时处理较为繁重的现状，作者采用了现场可编程门阵列( fpga )加以解决。 |
| 8. | On the base of it , a piece of data collection special chip with a core of fft is designed with vhdl ( vhsic hardware description language ) in the way of top down system design method , which can finish harmonic analysis and measure the voltage , current , frequency and power of the electric power system
在此基础上，使用标准的硬件描述语言vhdl设计出一个fft变换内核，并以该内核为核心、采取自上而下的系统设计方法完成了一个电力系统数据采集专用芯片的设计，实现对电力系统的电压、电流、频率、有功和无功功率等参数的测量以及各次谐波分析。 |
| 9. | The relevant program of both the dongle and the computer have also been developmented . a parallel port and a serial port are provided for the pcb . there is a program ( in vhdl , vhsic hardware description language ) carrying out in the pld which implementi ng the parallel protocol . an encrpt arithmetic is designed and embeded in pld . to providing a interface for the user , a dll ( dynamic link library ) is developmented in c + + builder
所设计的电路板上可以选择连接串行口或者并行口，在pld内用vhdl ( vhsichardwaredescriptionlanguage ，硬件描述语言)实现了并口的通信协议和一个自行研制的密码算法，并在c + + builder环境下开发了配套的上位机软件，主要是提供了dll (动态链接库)和一些函数用于pc机和加密锁之间进行通信。 |
| 10. | The key to the fft algorithm is the design of butterfly computation and that of the address logic . the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ) , basing on these , we do our research on reconfigurable technology . the result indicates that the data processing ability of reconfigurable system improved greatly
结果表明，可重构系统在数据处理能力方面比以往的系统有了很大的提高，本设计实现的fft重构处理器可工作于60mhz下，完成一个16点fft需要132个主时钟周期，完成32点fft需要324个主时钟周期，而且具有一定可重构性，可以方便地将其运算点数进行扩展，或将其他的图像处理算法在实时处理系统中实现。 |
