To increase hardware utilization and minimize cost , we combine inter and intra prediction by a reprogrammable fir filter , which is further implemented with systolic array 利用在解码的过程中一个巨块不会同时利用到内部以及相互预测的特性，设计了一套既可以处理内部预测也可以处理相互预测单一硬体架构来增加硬体使用效率以及降低成本。
2.
The simulation in quartusii for the blocks with fpga is proposed at last . compare with the traditional polarization diversity and combining receiver , the stability of the scheme proposed in this paper is better , the parameter of it is reprogrammable , and upgrading of the system is also easily . then the diversity 与传统的极化分集接收机相比,利用本文提出的系统设计方案设计的数字极化分集接收机具有工作更稳定,参数可编程以及便于系统升级等优点,这样就使得在一个硬件平台上实现不同参数分集接收成为可能。
3.
In order to resolve the contradiction between real - time and arithmetic complex in the television tracking capture system , the paper designs the real - time target track processing system which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor , the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image 摘要为解决电视捕获跟踪瞄准系统中系统的实时性与算法复杂性之间的矛盾，设计了以高性能的dsp芯片tms320c6416为核心处理器，结合大规模可编程逻辑器件cpld进行逻辑控制以及现场可编程门阵列fpga对采集的视频数字图像做预处理的实时目标识别跟踪处理平台。
4.
The real - time target track processing system is designed which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor , the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image 为了解决算法复杂性及满足工程实时性，设计了以高性能的dsp芯片tms320c6416为核心处理器，结合大规模可编程逻辑器件cpld进行逻辑控制以及现场可编程门阵列fpga对采集的视频数字图像做预处理的实时目标识别跟踪处理平台。
