| 1. | Furthermore , timing simulation and static - state timing analysis were made . by doing these , netlist files were got
并进一步做时序仿真和静态时序分析,产生输出网表文件,最后下载到fpga进行系统实现。 |
| 2. | The effects of the time sequence netlist simulation of the circuit and fpga verification indicate the correctness of the circuit design
行为仿真结果、综合布线后的门级仿真结果以及fpga验证结果均表明了设计的正确性。 |
| 3. | This tool could analyze the connection relationship between the submodels of the system designed with simulink and give out a verilog hdl description of the netlist
它可以对simulink中顶层的各个模块之间的连接关系进行分析,并将分析的结果用veriloghdl描述出来。 |
| 4. | At last , eda tools generate netlist for semiconductor manufactory . the eda technology and veriolog hdl must speed up the design of risc cpu in china
高性能精简指令集微处理器的设计通过运用veriloghdl语言， eda工具，和asic设计的主要流程，缩短了设计周期，加快其产品的面市速度。 |
| 5. | According to the hardware structure of the main experiment board , the circuit netlist transformation program translates the visual circuit description to the actual netlist
根据实验主板的硬件结构，设计的专用电路网表转化程序，将便于用户理解的图形化的电路描述转化为便于实际硬件操作的电路网表。 |
| 6. | It induces logic and delay to waveform , and describes the continuous states of nodes in netlist by waveform . it can realize simulating continuous states for integrated circuits by computing waveforms
它把逻辑和延迟有机地结合起来归纳为波形，并用波形来描述电路网表中节点的连续时间状态，通过对波形的计算实现整个电路的连续时间状态模拟。 |
| 7. | Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist , so for obtaining correct simulation result , i must have logic computing correctly and delay analysis accuracily
由于数字电路的模拟是基于对电路网表中的元件进行逻辑和延时计算的，所以要想得到正确的模拟结果，必须进行正确的逻辑运算和准确的延时分析。 |
| 8. | Recurring to the circuit netlist , the mcu of the main board finishes the digital setting for the parameters and the structure of the experiment circuit , which realize to do all kinds of electronics experiments in the same main experiment board
控制实验主板的单片机借助于电路网表所提供的信息，完成实验电路结构和参数的全数字化设置，从而实现了在同一实验主板上完成不同的电工电子实验。 |
| 9. | Then describes the 4 function modules in vhdl , the vhdl programs have passed compile and debug in maxplus ii , the results of function simulation and timing simulation all prove that the design is correct , at last , maxplus ii generates a netlist file which can be download into chip
然后使用vhdl硬件描述语言对四大功能模块进行描述，在maxplus环境下编译、调试通过，功能仿真和时序仿真结果证明设计正确，最后生成可下载的网表文件。 |
| 10. | It presents the verification strategy used in the whole eda design flow of the chip . the simulation on module level ( inc . post - layout ) uses the software event - driven simulator , the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator , for the gate - level netlist produced by using top - down design flow , the sta tool can analyze the static timing , and more formal verification is used to ensure the correct function
本章还提出了系统在整个eda设计流程中的设计验证策略方法：模块级的模拟(包括布线后的模拟)全部采用事件驱动式的软件模拟工具来验证，各大模块的联合模拟及整个芯片的功能验证(寄存器传输级与门级)使用基于周期的模拟工具和硬件仿真器；对于采用top - down的设计方法得到的门级网表使用专门的静态时序分析工具来进行时序分析以及采用形式验证来保证正确的功能。 |
