| 1. | Design of double - edge - triggered dynamic flip - flop and its application
双边沿动态触发器的设计及其应用 |
| 2. | A det ( double - edge - triggered ) shift counter designed with the det shift register is demonstrated
使用该移位寄存器设计双边沿移位计数器的实例被演示。 |
| 3. | Semiconductor integrated cicuits . detail specification for type jt54f74 fttl dual d positive edge - triggered flip - flops
半导体集成电路. jt54f74型fttl双上升沿d触发器详细规范 |
| 4. | To eliminate the bootless power dissipation of the redundant transition of the clock , a design method named det ( double - edge - triggered ) shift register is proposed
摘要从消除时钟信号冗馀跳变而致的无效功耗的要求出发，提出双边沿移位寄存器的设计思想。 |
| 5. | Then , we propose a design method named det ( double - edge - triggered ) shift register to eliminate the bootless power dissipation of the redundant transition of the clock
接着，从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出双边沿移位寄存器的设计思想。 |
| 6. | According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
为消除时钟信号的兀余跳变，提出了利用时钟两个方向跳变的双边沿触发器逻辑发计并应用于时序电路设计中。 |
| 7. | From the concept of triditional master - slave flip - flop , we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input
并且从传统主从结构触发器出发，提出了简化结构的维持阻塞型触发器设计。针对数字电路中大量存在的冗余现象，本文讨论了冗余抑制原理以及相应的冗余抑制技术。 |
| 8. | Based on the construction of traditional flip - flop , we propose a novel edge - triggered flip - flip using one latch controlled by narrow pulse according to race - hazard of clock . then this principle is adopted in ternary circuit , a new ternary d type edge - triggered flip - fiop based on cmos transmission gate is proposed
在二值单闩锁结构边沿触发器的基础上，把利用时钟信号竞争冒险的思想应用于三值电路中，提出了基于cmos传输门的二值d型时钟信号竞争型边沿触发器。 |
