总线接口时序 meaning in English

bus interface timing

During the design of vxi - bus serial controller module , the functions of vxi - bus including time - sequence for vxi interface , resource management , interrupt process , bus arbitration , are accomplished . to advance the performance and stability , the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence , the uart , the parameterized baud generator and “ pipeling frame ” . the handle type of data transfer bus for vxi - bus is researched thoroughly , and the format of serial data transfer is designed
在vxi总线串行控制器设计中,实现了vxi总线控制器的基本功能,包括vxi总线接口时序、总线仲裁、超时处理等;同时利用先进的fpga技术实现了串行总线时序向vxi总线时序的转换、通用异步收发器( uart ) 、参数化波特率发生器、流水线结构等功能模块;在设计中还深入研究了vxi总线数据传输的各种操作类型,制定了串行数据传输的编码格式。