logic block meaning in Chinese
逻辑区段
Examples
- Base on the analysis of comparison to current file systems , this thesis proposes new distributed network file system architecture on the tcp / ip protocol . the newly proposed file system is a three - layer architecture including clients , index servers and logic block servers
本文在分析现有的网络文件系统的基础上，提出一种基于tcp ip的分布式网络文件系统结构，即以客户端、索引服务器和逻辑块服务器为基础的三层结构。 - Researched the methods to test configrable logic block ( clb ) and its sub - blocks . based on a “ divide and conquer ” methodology , the clb resources are divided into three basic blocks : logic units , carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode . the testing configurations are implemented based on a two - dimensional array structure for logic blocks
主要基于“分治法”对clb及其子模块进位逻辑( clm ) 、查找表( lut )的ram工作模式等进行了测试划分,分别实现了以“一维阵列”为基础的测试配置和测试向量,以较少了测试编程次数完成了所有clb资源的测试。 - Through the implementing of kernel level file and cache mechanism at the client side , this newly proposed distributed network file system provides seamless network file access and reduces the performance decline caused by network transmission . utilizing the concept of logic block server , it provides the reliable data block storage and implements redundant storage capacity . utilizing the concept of the index server , it provide s the cost of the greatly for server and network during data access process and realizes the computing with balancing capacity
在客户端通过实现内核级文件的调用和缓冲机制，实现了文件的无缝网络存取，并减少由于网络传输带来的性能下降的影响；利用逻辑块服务器实现逻辑块的冗余存取，实现数据块的安全存放；利用索引服务器进行负载均衡计算，实现资料存取的较低网络和服务器开销；利用索引服务器实现服务器组的零管理，使该系统具有高效性、稳定性和可伸缩性。 - However , in most published works , only the diagnosis of logic blocks is discussed . the diagnosis of fault routing network is considered in some cases , where switching matrices are diagnosed individually . an fpga usually consists of complicated routing structure , it may not be easy to apply tests to individually components
本文概述了已有fpga连线结构的一些测试技术，结合以前的fpga的诊断与测试技术，提出了通过讨论开关矩阵及其连线的一个可行的测试及诊断方法，由七个测试阶段，分别讨论了fpga开关矩阵中各开关与相关连线的各种可能发生故障的情况，通过施加相应的测试信号序列来对连线资源的故障情况进行较完全的测试。 - The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length . the performance of mcu has been improved greatly by introducing single - clock - cycle instructions , setting multiple high - speed working registers and replacing micro - program with direct logic block etc . to keep the mcu core reusable and transplantable , the whole mcu core has been coded for synthesis in verilog hdl
该mcu核采用哈佛结构、 16位指令字长和8位数据字长，通过设计单周期指令、在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法，加快了微处理器的速度，提高了指令的执行效率。