设计输入 meaning in English
design capture
Examples
- In this article , we study the implemetation of fpga for elliptic curve digital signature algorithm . based on number thesis 、 abstract algebra and complex thesis ， integrated information theory 、 cryptography and some specific relevant algorithm ， we ascertain the implementation of ecdsa for hardware project ： according to the design idea of hiberarchy and modularization , we adopt very high speed ic hardware description language ( vhdl ) as design input and simulate the design in every level and every model for the correct of the fundamental design . after finish the top design , we perform the whole simulation . then ， we carry out the timing simulation after the logic synthes and layout
本文从实际应用出发，研究了椭圆曲线数字签名算法的fpga的实现：以基本的数论理论、抽象代数和复杂度理论为依据，结合信息论、密码学的一些知识以及一些具体的相关算法，确定了ecdsa的硬件实现方案：按照层次化、模块化的设计思想，采用硬件描述语言vhdl作为设计输入进行ecdsa的硬件设计；在每个设计层次和每个模块都进行了仿真验证，得以保证底层设计的正确性。在确保每个模块的设计正确后，完成对电路的顶层设计，进行总体的仿真。 - Mostly , this design employs mentor corporation software " fpga advantage " as exploitation tool to perform design input 、 simulation and logic thesis with every level and every model to finish the fore design ； then , choices the xilinx corporation product xcv1000 of the vertex series and employ its tool “ allicance series ” to implement layout and timing simulation
设计主要采用menter公司的功能强大的fpgaadvantage作为开发工具，进行了各个层次、各个模块的设计输入、仿真以及逻辑综合，完成了电路的前端设计；然后选用xinlinx公司的fpga的vertex系列的xcv1000 ，用xinlinx公司的allianceseries工具，进行布局布线，然后再进行时序仿真，生成配置文件。 - The design of this chip sticks to the general methodology of hdl design . lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator , after synthesized with fpga compiler ii , the edif is entered in quartus ii , which is supplied by altera corporation to place and route . the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done . the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl
在innoveda的visualhdl设计平台上用hdl语言完成了设计输入，使用modelsim仿真器完成了功能仿真，使用synopsys的fpgacompiler进行了基于alterafpga库的网表综合，最后将edif网表输入altera的布局布线工具quartus中进行了布局布线，将生成的sdo文件反标到modelsim仿真器中进行了时序仿真，该设计的成功，再一次表明了hdl设计方法的正确性和有效性。 - The thesis has done the widespread investigation and study to the domestic and foreign ’ s technologies of analogy low voltage and low power , and analyzes the principles of work , merts and shortcomings of these technologies , based on the absorption of these technologies , it designs a 1 . 5v low power rail - to - rail cmos operational amplifier . when designing input stage , in order to enable the input common mode voltage range to achieve rail - to - rail , it does not use the traditional differential input pair , but use the nmos tube and the pmos tube parallel supplementary differential input pair to the structure , and uses the proportional current mirror technology to realize the constant transconductance of input stage . in the middle gain stage design , the current mirror load does not use the traditional standard cascode structure , but uses the low voltage , wide - swing casecode structure which is suitable to work in low voltage . when designing output stage , in order to enhance the efficiency , it uses the push - pull common source stage amplifier as the output stage , the output voltage swing basically reached rail - to - rail . the thesis changes the design of the traditional normal source based on the operational amplifier , uses the differential amplifier with current mirror load to design a normal current source . the normal current source provides the stable bias current and the bias voltage to the operational amplifier , so the stability of operational amplifier is guaranteed . the thesis uses the miller compensate technology with a adjusting zero resistance to compensate the operational amplifier
本论文对国内外的模拟低电压低功耗技术做了广泛的调查研究,分析了这些技术的工作原理和优缺点,在吸收这些技术成果基础上设计了一个1 . 5v低功耗轨至轨cmos运算放大器。在设计输入级时,为了使输入共模电压范围达到轨至轨,不是采用传统的差动输入结构,而是采用了nmos管和pmos管并联的互补差动输入对结构,并采用成比例的电流镜技术实现了输入级跨导的恒定;在中间增益级设计中,电流镜负载并不是采用传统的标准共源共栅结构,而是采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了推挽共源级放大器作为输出级,输出电压摆幅基本上达到了轨至轨;本论文改变传统基准源基于运放的设计,采用了带电流镜负载的差分放大器设计了一个基准电流源,给运放提供稳定的偏置电流和偏置电压,保证了运放的稳定性;并采用了带调零电阻的密勒补偿技术对运放进行频率补偿。 - The resonance network is connected to the gate , then the output and input matching network is designed to satisfy the oscillation criteria . then harmonic balance method is used to analysize and optimize the output power and phase noise . to minimize the load pulling effect a buffer amplifier is designed to isolate the oscillator and the load
本文在场效应管fet栅极上加上谐振网络(谐振网络是通过cst仿真得到的,它是串联反馈回路,介质工作在te01模,对于其后的fet ,它又相当于一个带阻滤波器) ,然后设计输入输出匹配电路,使电路结构满足起振条件,之后继续用谐波平衡法仿真和优化,使振荡器输出功率合适,相位噪声很低。