Chinese translation for "总线时序"

bus timing

Related Translations:

时序效应:  time order effect

总线输入总线:  bus-in bus

指令总线:  instruction bus

加法总线:  add busbus, summingsumming bus

供水总线:  service main

视频总线:  video bus

浮动总线:  floating bus

总线接插件:  bus connector

总线驱动器:  bd bus driverbus driver

扩充总线:  expa ion bus

Example Sentences:

	1.	During the design of vxi - bus serial controller module , the functions of vxi - bus including time - sequence for vxi interface , resource management , interrupt process , bus arbitration , are accomplished . to advance the performance and stability , the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence , the uart , the parameterized baud generator and “ pipeling frame ” . the handle type of data transfer bus for vxi - bus is researched thoroughly , and the format of serial data transfer is designed 在vxi总线串行控制器设计中,实现了vxi总线控制器的基本功能,包括vxi总线接口时序、总线仲裁、超时处理等;同时利用先进的fpga技术实现了串行总线时序向vxi总线时序的转换、通用异步收发器( uart ) 、参数化波特率发生器、流水线结构等功能模块;在设计中还深入研究了vxi总线数据传输的各种操作类型,制定了串行数据传输的编码格式。
	2.	The subject has mainly finished designing and debugging software and hardware of a / d decode module , fpga video processing module , video data frame deposit module , base clock produce module , d / a encode module , i2c bus control module , etc . a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing 本课题主要完成了a d解码模块、 fpga视频处理模块、视频数据帧存模块、基准时钟产生模块、 d a编码模块、 i ~ 2c总线控制模块等部分软、硬件设计及调试。其中a d解码模块采集模拟电视信号实现视频解码； fpga视频处理模块对解码后的数据进行去噪处理的同时还负责系统的逻辑控制；视频数据帧存模块为大量高速的视频数据提供缓冲区；基准时钟产生模块通过输入基准视频信号为系统提供精确的相关同步信号； d a编码模块在视频处理模块的控制下把数字视频数据转换成复合电视信号供显示用： i ~ 2c总线控制模块模拟i ~ 2c总线时序实现对系统中编、解码芯片的初始化。

Similar Words：

"总线上错误的电气类型" Chinese translation, "总线上的信元被信元地址筛选器" Chinese translation, "总线上升总线" Chinese translation, "总线设备请求" Chinese translation, "总线设置" Chinese translation, "总线时序仿真" Chinese translation, "总线时钟" Chinese translation, "总线时钟，总线定时" Chinese translation, "总线时钟频率" Chinese translation, "总线使用量" Chinese translation