连线延迟 meaning in Chinese

wiring delay

Interconnect wire delay questions in deep submicron ic design
深亚微米集成电路设计中的互连线延迟问题
This update fixes false error messages that occur when the latency of internet connections causes problems while adding time
网际网路连线延迟导致误时问题时将显示的false错误讯息，此更新可修正这个错误讯息。
When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
在深亚微米制造技术中，芯片互连线延迟超过门延迟，而且随着集成电路工作频率的提高，允许的时序容差变小，传输延迟的影响加大，设计工作难度增加。
When feature size comes to 0 . 35 m , interconnect delay has contributed 70 % to total delay . distribution of delay parameters lies on actual implementation of layout , which results in the fact that timing closure has become the chief problem . so synthesis technology must be based on timing to insure timing closure
特征尺寸进入0 . 35 m后，互连线延迟占到系统延迟的70以上，而延迟参数的分布又取决于版图的具体实现，导致时序收敛成为设计的首要问题，因此综合技术必须要基于时序，保证时序收敛。