软件模拟工具 meaning in Chinese

software simulation tool

It presents the verification strategy used in the whole eda design flow of the chip . the simulation on module level ( inc . post - layout ) uses the software event - driven simulator , the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator , for the gate - level netlist produced by using top - down design flow , the sta tool can analyze the static timing , and more formal verification is used to ensure the correct function
本章还提出了系统在整个eda设计流程中的设计验证策略方法：模块级的模拟(包括布线后的模拟)全部采用事件驱动式的软件模拟工具来验证，各大模块的联合模拟及整个芯片的功能验证(寄存器传输级与门级)使用基于周期的模拟工具和硬件仿真器；对于采用top - down的设计方法得到的门级网表使用专门的静态时序分析工具来进行时序分析以及采用形式验证来保证正确的功能。