芯片尺寸 meaning in Chinese
csb :chiscale ball grid array
Examples
- Ultrathin wafer level chip size package technology
超薄型圆片级芯片尺寸封装技术 - Ut - scsp ultra - thin - stacked chip size package
超薄叠层芯片尺寸封装 - This increase in chip size means that designs get more complicated because they must manipulate and hold larger systems called soc , or " system - on - chip " , designs
芯片尺寸的增加意味着设计工作将变得更加复杂，因为他们必须操作、控制更大的系统（称为soc或" system - on - chip "设计） 。 - As an advanced package , 3 - d stacked csp assembly provides significant size and performance advantages than traditional single chip package . meanwhile , high packaging density tends to generate more power in a package and cause serious thermal problem
三维叠层芯片尺寸封装( stackedchipscalepackage )是目前最先进的微电子封装形式之一,具有体积小、重量轻、封装效率高等特点。 - According to process rules of the gaas mmic product line , we properly designed the circuit layout . in order to reduce the overall chip size , the transmission lines are folded with sufficient spacing to avoid interline coupling . the lange couplers are also folded to keep the 90 and 180 bits " sizes similar to other phase shift bits " sizes
结合实际mmic工艺线，合理设计移相器电路版图，折叠微带线并留出足够大的线间距，以避免线间寄生耦合的发生，并折叠兰格耦合器使90和180移相位的尺寸与其它相位的芯片尺寸保持一致。