耦合电容 meaning in Chinese
coupled capacitor
coupling capacitance
coupling capacity
Examples
- Hierarchical extraction of global capacitance matrix for 3d vlsi interconnects
三维互连全耦合电容矩阵的层次式提取算法 - 2 gao t , liu c l . minimum crosstalk channel routing . in proc . the ieee int
对于减少耦合电容的方法可以通过线网排序使敏感线网不相邻来实现。 - 16 lin s , chang n , nakagawa o s . quick on - chip self - and mutual - inductance screen . in proc
同时插入屏蔽和线网排序是一种减少耦合电容和耦合电感噪声的有效方法。 - Eda lab , department of computer science and technology , tsinghua university , beijing 100084 , p . r . china
耦合电容和耦合电感导致的信号线互相影响的效应称为串扰。 - First , the capacitor inserted allows a low frequency " extension " due to the resonance between the transformers inductance and the capacitance value
第一，耦合电容和变压器初级电感之间的谐振可以容许更好的低频延展。