硬件语言 meaning in Chinese
hardware language
Examples
- The thesis is a research of the pic microcontroller of microchip corporation . the thesis includes a design of a cpu ip core with verilog hdl , and the design bases on up - down design flow
首先从正向设计和仿真的角度，给pic微控制器中的核心部件-处理器单元建立了一个硬件语言描述的ip模型。 - The aim of this paper is to implement the decoder of turbo codes with fpga . the iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper
本文以turbo码译码器的fpga实现为目标,对turbo码的迭代译码算法及用硬件语言实现其译码算法进行了深入研究。 - The second part studies the characteristics of cdma2000 1x reverse link , and implements a softcore design of the cdma20001x rtl soc with hdl ( hardwire desciptionin language ) verilog in accordance with the is - 2000 specifications . the model include the softcore of a spread spectrum modulation and a simple 8 - bit processor . as the same time simulate all the parts of the soc softcore with software modesim
，本文的第二部分认真的研究了cdma20001x的反向链路的特点，设计反向链路的扩频调制片上系统方案。用硬件语言verilog设计cdma20001x的扩频调制片上系统的ip软核。其中包括扩频调制部分和一个8位的cpu设计。 - This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。 - We choose the max _ log _ map decoding algorithm and use the technology of altera and its cyclone2 devices as the fpga design scheme according to all the factors . taking advantage of the technology of fpga , the means , called “ top - down ” and “ down - top ” , is applied in the design of fpga in this paper
在综合考虑设计方案的综合性能、复杂程度、系统规模、系统延时和成本等各项因素后,本次设计选择了altera公司的cyclone2器件来完成turbo码译码算法( max _ log _ map )在硬件语言上的仿真设计。