硅栅 meaning in Chinese
silicon gate
Examples
- A breakdown model of thin drift region ldmos with a step doping profile
器件多晶硅栅量子效应的解析模型 - Applying silicon gate technology , the chip has a lower value in power consumption than the products made by aluminum gate technology
由于采用硅栅工艺，该芯片比市场上曾经流行过的铝栅产品功耗更低。 - In the paper , we introduced how to draw layout based on the standard of 0 . 6 m , 5v cmos given by csc semiconductor ltd and finish the work in candence
芯片版图的设计中采用了绿华半导体公司的0 . 6 m , 5vcmos工艺库,工艺基本特征为多晶硅栅,单层金属布线。 - Secondly , the radiation effects of the system of silicon gate si / sio2 ( silicon gate nmos and pmos ) implanted bf2 are made a deep systematic study . especially , the relationship between threshold voltage shift ( vth and vit vot ) in radiated mos transistor and irradiation dose rate , irradiation dose , irradiation temperature , bias voltage , device structure as well as annealing condition is explored emphatically
在此基础上，对bf _ 2 ~ +注入硅栅si sio _ 2系统低剂量率辐照效应进行了深入系统的研究，着重研究了bf _ 2 ~ -注入mos管阈值电压漂移( vth和vit 、 vot )与辐照剂量率、辐照总剂量、辐照温度、偏置电场、器件结构以及退火条件的依赖关系。 - Wirings of the poly layer are always utilized under the silicon grid technics . to control the macro - cell signal delay and improve signal integrality , the crossing among different nets must be averagely distributed to reduce the number of layer permutation . the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized
硅栅工艺晶体管级布线利用多晶层走线，为了控制宏单元时延性能及改善信号完整性形态，关键是不同线网间交叉的均衡分配以减少走线的换层次数，最大化金属层走线以及每一线网多晶层走线长度的有效控制。