操作时序 meaning in Chinese

time sequential routine
timesequentialroutine

After the designing was finished , the instruction system and operating scheduling were given
设计完成后，给出了单片机的各种操作时序以及指令系统。
On the base of investigating the properties of pci address / data bus and the sequence of read , a re - use model of pci address / data bus is proposed
讨论了pci接口ad双向总线及pci接口读操作时序的特性。提出了pciad总线再复用模型。
Based on the realization of the encoder / decoders , this scheme aims at the highest rate downstream frame , and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation . the fprme decoder is advanced in the world . the parallel fec circuit completely conforms to the itu - t protocols , and has important practical value
在rs ( 255 , 239 )硬件编码器/解码器实现的基础上,本文按照gpon协议要求,针对gpon中最高速率2 . 488gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行fec编解码和解扰码电路,并作了仿真。