总线寄存器 meaning in Chinese

bus register

The integrated register based vxibus interface is designed by using the advanced cpld technology . this method simplifies the interface circuit design and improves its reliability . 2
利用cpld技术自行设计了vxi总线寄存器基集成化接口电路和数据采集控制电路，从而简化了电路的设计，提高了可靠性。
After analyzing and digesting register - based interface circuit designed by predecessor , this paper designs register - based interface circuit of speed test module and programs instrument
在分析消化了前人设计的vxi总线寄存器基接口电路的基础上，设计了测速仪模块的寄存器基接口电路，编写了仪器驱动程序。