延时模型 meaning in Chinese
time delay model
Examples
- In this paper , several delay models have been provided and the results have been compared with the simulation to derive the accuracy of the models
本文就提出了简单的rc延迟模型和复杂的rlc互连延时模型，将模型的结果与hspice模拟结果进行比较分析，验证了模型能够比较精确的计算延迟时间。 - Through the simulation and calculation of the delay models , the improvement degree of the new material and geometric parameters for the interconnect delay can be concluded and performance optimizations should be made by analyzing these influences
而通过互连延时模型的模拟与计算，得出新材料即铜和低k介质对延时的改善程度，及互连线的几何参数对互连延时的影响，并根据这些确定最优尺寸来适应集成电路设计的需要。 - However , some improvements have been made for the distributed rc model , the precision ca n ' t attain the request due to the influence of parasitic effect especially the increasing inductance with the development of interconnect technologies in deep - submicrometer region . so these influences must be taken into consideration and the building of new distributed rlc model for interconnect delay and crosstalk becomes more importance . according to this model , two cases , that is , cmos driving transmission line and interconnect line between chips have been analyzed
对传统的分布rc模型进行了改善，但随着互连向深亚微米级发展，寄生效应的影响尤其是电感的影响，必须考虑，因此建立新的rlc传输模型是很必要的，本文提出了这种新的互连模型，并对cmos驱动互连线和芯片之间互连两种情况进行了分析，验证了延时模型是可靠和精确的，并对延时的改善起到了指导作用。 - Then studis on new models and new approaches based on boolean process in delay automation are made . analytical delay model is improved with the new concept of sensitization , based on which delay matrix is proposed to describe the delay of circuit modules . then introducing hierarchical delay analysis methods into delay matrix analysis , a novel exact hierarchical delay ananlysis method is presented
在组合逻辑电路精确定时方面，本文用波形多项式偏导定义的敏化概念改进了解析延时模型，在此基础上建立了基于敏化的延时矩阵以描述电路模块的延时，随后将层次化延时分析方法引入基于延时矩阵的延时分析中，形成一种新的精确的通用电路层次化延时分析方法。