字锁 meaning in Chinese
letter lock
Examples
- The essential theory of analog phase lock loop ( apll ) and digital phase lock loop ( dpll ) are introduced
然后介绍了模拟锁相环和数字锁相环技术,并对数字锁相环的稳定性和稳态误差性能进行了分析。 - We design the digital phase - locked loop applying the method designing digital circuitry from the top down . we design the circuitry by the vhdl in the maxpulsii software environment . we validate the circuitry function in the emulator
采用自顶向下的数字电路设计方法设计全数字锁相环路，在maxplusii设计环境下采用vhdl语言、 ahdl语言等设计实现数字锁相环，并通过计算机仿真证实其正确性。 - In the course of the design , critical technologies are applied , such as digital phase - locked loop , fast fourier transform algorithm , universal asynchronous receiver & transmitter , and so on . in the project , as a important component , the module of monitoring the buses " power quality takes a long time
在设计过程中，使用的关键技术有：使用cpld仿真多路sspc多种状态；在对汇流条电能质量的监测过程中采用频率跟踪技术? ?全数字锁相环；应用fpga技术使用fft运算进行谐波分析；通用异步收发器等技术。 - The main contributions of the dissertation are as follows : first , based on some results which have been made , by the used of the analogy pll and the digital pll , i ameliorates a precept of the mm frequency synthesizer , by this way i develop an mm frequency synthesizer , which can feed the request of some project
本论文的主要贡献在于:在前人所做工作的基础上,综合了模拟锁相技术和数字锁相技术的优点,对一种毫米波频综的设计方案加以改进,并根据改进后的方案研制出毫米波频综,其性能指标基本满足了某工程预研的设计要求 - The fourth , mainly talk about the phase noise in the pll , and discuss the specific affect on out put phase noise caused by different components in frequency synthesizer , such as mixer , amplifier , multipler , divider , oscillator , phase detector etc . the last part is about how to choice the natural frequency of pll in order to get the better performance in phase noise
第二章从锁相环的基本原理出发,介绍了锁相环的几个基本部件:鉴相器?环路滤波器和压控振荡器,对线性化锁相环进行了详细的分析,对数字锁相环做了详细的介绍,分析了锁相环的相位噪声模型,讨论了频综中的混频器