压缩电路 meaning in Chinese
compression circuit
Examples
- Time - base pressing circuit
时基压缩电路 - Yu hu , yinhe han , huawei li , tao lv , and xiaowei li , " pair balance - based test scheduling for socs " ， in : proc . of ieee asian test symposium ( ats ) , nov . 2004 , pp . 236 - 241
董婕，胡瑜，韩银和，李晓维， "基于组合解压缩电路的多扫描链测试方法" ，计算机研究与发展，已录用。 - The experimental results illuminate the hierarchical test generation algorithm can greatly decrease the scale of test sets ( about 66 % ) , but the fault coverage and time performance are lower than gate - level test generation
实验数据表明分层测试产生算法能大大压缩电路测试集（约为66 ） ，而故障覆盖率有略微下降，时间性能也有些许降低。