主时钟 meaning in Chinese
master timer
mc master clock
mclk
primary clock
Examples
- Master clock , microprocessor
微处理机主时钟 - Master clock frequency
主时钟频率 - Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains . the data transaction protocol comes from the most basic work way of uart . when the master clock is 16 . 7mhz , the pcm side and adpcm side clocks both are 2 . 38mhz , the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14 . 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14 . 7 us
在主时钟为16 . 7mhz ， pcm数据端与adpcm数据端时钟均为2 . 38mhz时，模拟结果表明从pcm的起始位输入uart接收器到adpcm终止位输出uart发送器的最大延迟为14 . 3 s ，从adpcm的起始位输入uart的接收器到pcm终止位输出uart发送器的最大延迟为14 . 7 s ，设计时尽可能的使编码与解码的时间相差不多，从结果看出基本达到这个要求。 - The key to the fft algorithm is the design of butterfly computation and that of the address logic . the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ) , basing on these , we do our research on reconfigurable technology . the result indicates that the data processing ability of reconfigurable system improved greatly
结果表明，可重构系统在数据处理能力方面比以往的系统有了很大的提高，本设计实现的fft重构处理器可工作于60mhz下，完成一个16点fft需要132个主时钟周期，完成32点fft需要324个主时钟周期，而且具有一定可重构性，可以方便地将其运算点数进行扩展，或将其他的图像处理算法在实时处理系统中实现。