netlist meaning in Chinese
排线表列
Examples
- Furthermore , timing simulation and static - state timing analysis were made . by doing these , netlist files were got
并进一步做时序仿真和静态时序分析,产生输出网表文件,最后下载到fpga进行系统实现。 - The effects of the time sequence netlist simulation of the circuit and fpga verification indicate the correctness of the circuit design
行为仿真结果、综合布线后的门级仿真结果以及fpga验证结果均表明了设计的正确性。 - This tool could analyze the connection relationship between the submodels of the system designed with simulink and give out a verilog hdl description of the netlist
它可以对simulink中顶层的各个模块之间的连接关系进行分析,并将分析的结果用veriloghdl描述出来。 - At last , eda tools generate netlist for semiconductor manufactory . the eda technology and veriolog hdl must speed up the design of risc cpu in china
高性能精简指令集微处理器的设计通过运用veriloghdl语言， eda工具，和asic设计的主要流程，缩短了设计周期，加快其产品的面市速度。 - According to the hardware structure of the main experiment board , the circuit netlist transformation program translates the visual circuit description to the actual netlist
根据实验主板的硬件结构，设计的专用电路网表转化程序，将便于用户理解的图形化的电路描述转化为便于实际硬件操作的电路网表。