高速数据传输系统 meaning in English
rapid transmission data system
Examples
- Therefore this thesis focuses on the research and design of high - powerful interface circuits for gigabit transceiver
本文致力于千兆位高速数据传输系统接口电路的研究和设计。 - After compare kinds of design , the ofdm knowledge be adopted to use in high - speed data transmission system and this system has been designed
系统物理层的设计，通过几种方案的对比，设计出采用ofdm技术的高速数据传输系统。 - The main works of the dissertation is to study a kind of adaptive equalization based on fast qr - decomposition . the study result will be applied to the 45m high - speed wireless communication system
本文的主要内容是研究基于快速qr分解的自适应均衡技术,研究成果将直接应用于45m无线通信高速数据传输系统中。 - The thesis is composed of 9 parts : the background , significance , main topics and innovations in the thesis are introduced in chapter 1 ; in chapter 2 , the main function and performance of interface circuits are described from the view of system by using the example of gigabit ethernet ' s transceiver ; the transmission media ' s frequency characteristics and model are analyzed for the high - speed data transmission system in chapter 3 ; the line driver is presented in chapter 4 ; the equalization principles for high - speed data transmission system are introduced in chapter 5 ; a novel adaptive equalizer for 1000base - cx transceiver is presented in chapter 6 ; in chapter 7 , a fixed equalizer for 2 . 5gbps transceiver is described ; in chapter 8 , layout design and measured results are discussed ; at last , the conclusions are drawn in chapter 9 . during period of finishing the thesis , i read lots of literatures about the interface circuits in high - speed data transmission system , studied their principles and design techniques , and designed : 1 、 the line driver for 2 . 5gbps baseband copper cable transceiver ; 2 、 the fixed equalizer for 2 . 5gbps baseband copper cable transceiver ; 3 、 the fixed equalizer for 1 . 5gbps sata ( serial at attachment ) transceiver ; 4 、 an adaptive equalizer for 1000base - cx transceiver
论文由9部分组成：在第一章引言中介绍了论文的背景、意义、国内外研究现状，以及论文的主要内容和创新；第二章以千兆位以太网为例，从系统的角度介绍了高速数据传输系统接口电路的主要功能和性能指标；第三章分析了高速数据传输系统的传输介质的频率特性和模型；第四章描述了线驱动器的设计原理及其电路实现；第五章描述了高速数据传输系统的均衡原理；第六章描述了适用于1 . 25gbps基带铜缆收发器系统的自适应均衡器的设计原理和电路实现；第七章描述了适用于2 . 5gbps基带铜缆收发器系统和1 . 5gbps串行硬盘接口( sata )收发器系统的固定均衡器的设计原理及其电路实现；在第八章中分析了电路的版图设计及芯片测试结果；最后，第九章总结了全文。在完成论文期间，查阅了大量的有关高速数据传输系统接口电路方面的文献，较系统地学习了线驱动器、传输线和均衡器等方面的理论知识和电路设计原理，设计了用于： ( 1 ) 2 . 5gbps基带铜缆收发器系统的线驱动器； ( 2 ) 2 . 5gbps基带铜缆收发器系统的固定均衡器； ( 3 ) 1 . 5gbpssata系统的固定均衡器； ( 4 ) 1 . 25gbps基带铜缆收发器系统的自适应均衡器。