模块逻辑 meaning in English
module logic
Examples
- Each logic module was verified by simulation
通过仿真，验证了各个模块逻辑设计的正确性。 - A complete vvp instrument consists of one enhanced main board and several plug - in boards , which is suitable for constructing basic instruments ( no cpu ) , typical instruments ( a single cpu ) and advanced instruments ( multi - dsp )
本章详细阐述了vvp平台的设计思想、体系结构以及vvp控者模块逻辑设计的实现。 - Simulations are executed in altera ’ s quartus ii environment with altera ’ s stratix family fpgas using verilog hdl after analysis . the results show that the sfn adapter can properly insert mip into transport stream and the time to be delayed in sync system can be correctly calculated and carried out with fifo
在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个单频网适配器进行了仿真。 - Concretely , on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ) , the standard and the module application of dsp and cpld , the thesis has proposed the design of the arinc 429 technology based on dsp system . at first , the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced . secondly , the hardware structure of the interface module is described in detail , mainly including data latch and buffer circuit , choice circuit of transmission rate , etc . and then the design philosophy and flow charts of the software are fully discussed , such as the basic requirement of software , the design and realization of the function
本文在简单的论述了pc并口协议( epp )与dsp之间的通信方法、 cpld模块逻辑控制应用和arinc429的通讯规范的基础上,给出了基于dsp的arinc429通讯接口的设计方案:对通讯板中各模块的功能和应用以及构成数据转换主体的总线接口芯片hs - 3282的工作原理做了说明;介绍了本设计所用的dsp和cpld的功能概况;详细叙述了通讯板接口模块的硬件结构设计,其中,对数据缓冲电路、数据传输速率选择电路、逻辑控制电路等各关键点做了重点介绍;具体阐述了软件设计思想及流程图,包括软件的基本要求和功能的设计与实现;接着从端口译码单元、 i / o通道、电平转换电路等方面进行了接口模块的软、硬件调试;最后,给出了测试结果,对研制工作做了总结,对本设计的优缺点各做了评述。 - According to the function of test platform , the test platform is partition into a few modules . those modules are designed with verilog hdl and the key problems are discussed in details . the verilog codes for transmit and receive end of test platform are simulated under quartus ii 5 . 0 ise , and debugged by downloading the verilog programs into ep1s25f780c and ep1s80b956c6 developing kits
在对每一个模块的设计要点做了详细说明之后,采用verilog语言编写各模块逻辑代码,在altera公司的quartusii5 . 0集成开发环境下,基于altera公司stratix系列fpga对各模块及整个窄带ldpc解码-误码测试平台进行了仿真并将发端和收端的verilog程序分别下载到altera的ep1s25f780c和ep1s80b956c6开发实验板进行调试。