寄生电感 meaning in English
inductance, parasitic
parasitic inductance
spurious inductance
Examples
- An inductance extraction method for on - chip signal lines based on halo rules
规则的片内信号线寄生电感提取法 - 4 . the noise of the substrate and the inductors of the pads are investigated in detail
4 .研究了衬底噪声和焊盘寄生电感对电路的影响。 - With the kind of design of 0 . 5 - 6ghz wlna , a new type of amplifier with on / off function , based on sige device , is presented , which is improved by adopting parasitic parameter with sige hit - kit 0 . 35 m bicmos process . at present simulation is finished successfully , and the amplifier is coming to be commercialized
论文提出了具有开关功能的低功耗sige双极器件的新型放大器和利用寄生电感来设计电路的新思路,同时在工艺上采用sigehit - kit0 . 35 mbicmos工艺来制作平面电感和有源器件,成功完成了0 . 5 - 6ghz微波宽带低噪声放大器的前期仿真和设计工作。 - To make use of parasitic parameter to design the circuit : because parasitic inductance induced by packaging could not only influence the circuit characteristics , but also lead to a design failure , the inductor value needed in the circuit can be designed in the amplifier according to the size of parasitic inductance
4 、利用寄生参数来设计电路。由于电路的封装存在寄生电感,其不仅会影响电路的特性,而且可能造成电路设计工作的失败,所以根据电路所需电感及其值的大小,将之有效的设计在放大器电路中。 - In the design and debugging process we found that two different caps with parallel connection may make the amplifier instability . with the analyses of the nonideal cap molding we found that the response curve of two different caps with parallel connection has a saltation whose impedance is infinity and at this pot the amplifier is easy to oscillate . than some suggestion of the use of cap in amplifier design is presented
在放大器的设计、调试过程中发现两个不同容值的电容并联会带来电路的潜在不稳定,对实际电容,即带有寄生电感和寄生电阻的电容,建模、分析后发现,不同容值的电容直接并联其响应曲线会有一个阻抗值为无穷大的突变点,该突变点可能会引起电路的自激。