处理阵列 meaning in English

processing array

This design can provide a high - speed path to a set of sharc parallel array processor . between this parallel processor and an analog signal acquisition module , the designed system can realize real time transmission
本设计的目的在于为一套sharc并行处理阵列机提供高速的数据通道，使其能与模拟信号采集模块进行实时的数据传输。
10 wallner s . a configurable system - on - chip architecture for embedded devices . in ninth asia - pacific computer systems architecture conference acsac 2004 , beijing , china , springer , lncs 3189 , sept . 7 - 9 , 2004 , pp . 58 - 71 . 11 wallner s . design methodology of a configurable system - on - chip architecture
它结合了大量的宏模块资源，包括一个类标量处理器内核粗粒度可配置的处理阵列嵌入式的存储器，以及由微任务控制器mtc监控的定制模块。
The hardware has two input channels of high - speed analog signal , with the signal amplitude of 0 - 5v , the conversion precision of 12bits , and the maximum sampling rate of 400ksps . this system includes 4 dsps ( adsp 2181 ) , which can be arranged as a pipe line processing array . many algorithms can be realized in this system
系统硬件有两路模拟数据采集通道，模拟信号输入范围为0 ? 5v ，转换精度为12位，最高采样率400ksps ；系统包含4片dsp ( adsp2181 )构成的流水线型的处理阵列，可用于实现各种算法；系统的控制逻辑由fpga完成。