型触发器 meaning in English

d-fliflod

To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
为抑制时序电路中的冗余现象，研究了时序电路的门控时钟技术，并利用t型触发器进行时序电路设计。
On the other hand , the " for each statement " not allowed for " before " triggers would mean that the actions defined by a trigger would only be performed once for the invoking sql statement
另一方面， " for each statement "选项（ " before "型触发器是不允许的）则意味着触发器定义的操作只在调用一次sql语句后执行一次。
From the concept of triditional master - slave flip - flop , we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input
并且从传统主从结构触发器出发，提出了简化结构的维持阻塞型触发器设计。针对数字电路中大量存在的冗余现象，本文讨论了冗余抑制原理以及相应的冗余抑制技术。