位并行 meaning in English
bit parallel
bit-parallel
parallel bit
Examples
- Bit - parallel associative memory
位并行相联存储器 - The data transfer capacity ( in bits per second ) of a bit - parallel bus
每条位并行总线上可传输数据的容量,用比特秒表示。 - In this paper , we developed a self - assembly model for dna - based parallel addition . the central feature of this model is to apply the parallel logic . we make the complexity analysis of the algorithm used here
这里，提出了一种利用dna进行两个数的相加的模型，这一模型的思想是对两数逐位并行相加，极大地利用了dna计算并行的特点。 - Based on the realization of the encoder / decoders , this scheme aims at the highest rate downstream frame , and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation . the fprme decoder is advanced in the world . the parallel fec circuit completely conforms to the itu - t protocols , and has important practical value
在rs ( 255 , 239 )硬件编码器/解码器实现的基础上,本文按照gpon协议要求,针对gpon中最高速率2 . 488gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行fec编解码和解扰码电路,并作了仿真。 - The specific route is as follows : firstly , the output signals from the multipath sensor are nornalized , i . e . , all sensor signals ( including the analog data ) are transformed into multipath square wave pulse signals to form multipath parallel condition codes . these codes are treated as input signals for dac to obtain a series of dispersed analog signals for output as input signals for the vco . finally , a high frequency modulation signal is conducted at the vco ' s output
具体技术路线如下：先将由多路传感器输出的信号进行归一化处理，即将所有传感器信号(包括模拟量)转换成多路方波脉冲信号，以形成多位并行信号的状态码，将其作为dac的数据输入信号，从而得到一系列离散的模拟信号输出，作为vco的输入信号，最终在vco输出端形成高频的调制信号。