互补逻辑 meaning in English
complementary logic
complementarylogic
logic, complementary
Examples
- An error recoverable structure based on complementary logic and alternating - retry
基于互补逻辑和交替重试的差错恢复结构 - 25 orailov glu a . microarchitectural synthesis of gracefully degradable , dynamically reconfigurable asics for multiple faults . in proc
在无差错运行过程中， cl - acl结构按互补逻辑模式运行。 - Vlsi systems , 1998 , 6 : 58 - 66 . 24 kim k , karri r , potkonjak m . configurable space processors : a new approach to system - level fault tolerance . in proc
为了解决这一问题，本文又提出了一种新的使用互补逻辑-交替互补逻辑cl - acl切换模式的dmr结构文中称之为cl - acl结构。 - Circuit design is the basis of design of demultiplexer . speed , power and chip area are the main factors that should be considered in circuit design . every circuit structure has its merits and drawbacks , e . g . cmos logic family has a slower speed , but lower power , smaller area , scfl ( source couple fet logic ) family has a higher speed , but higher power , larger area . we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors . flip - flop is the fundamental element of demultiplexer , setup time and hold up time are key factors , which influence the speed of circuit , thus the design aim is how to reduce them . in this thesis we place emphasis on the design of scfl latches
速度、功耗、面积是电路设计要考虑的主要因素，不同的电路形式具有不同的优缺点，如cmos互补逻辑电路功耗低，面积小，速度相对较慢； scfl (源极耦合fet逻辑)电路速度高，功耗和面积较大。所以要针对具体设计需要选用适当的电路形式或其组合结构，以满足设计要求。触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了scfl锁存器的设计和优化方法。