ssram meaning in English

同步静态随机读写存储器

In this paper we use the bist in the testing of the ssrams in estarl according to the characteristics of the structure and get almost 100 % fault coverage
本文针对estar1内部ssram的结构特点，实现了存储器自测试，得到了将近100的故障覆盖率。
The cpu interface is the " bridge " between the ctu and cpu , which pass the configuration information to other modules in ctu , transfer the status information to cpu and test the ssram
Cpu接口作为通信网络处理器与cpu之间的桥梁，完成两者之间的信息传递。在此实现的功能有配置信息的下发、状态信息的上报、数据报文的上报以及片外ssram的测试等。